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The Implementation of Vedic Algorithms in Digital Signal Processing

A Time-Area- Power Efficient Multiplier

Speedy Deconvolution using Vedic Mathematics

Implementation of Vedic Multiplier for Digital Signal Processing

High Speed Reconfigurable FFT Design by Vedic Mathematics

A Digital Multiplier Architecture using Urdhva Tiryakbhyam

A Reduced-Bit Multiplication Algorithm for Digital Arithmetic

A New Square Root Algorithm for Large Number

A High Speed and Efficient Method of Elliptic Curve Encryption

Applied Geometry of the Sulba Sutras

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